Embodiments of the invention generally relate to deposition apparatus and methods of use. More specifically, embodiments of the invention relate to deposition apparatus which include a continuous grounded shield positioned outside a plasma source assembly.
Various deposition processes, including physical vapor deposition (PVD) and chemical vapor deposition (CVD) are used to deposit metal films such as copper onto semiconductor wafers to form electrical interconnections. In some PVD processes, a high level of D.C. power is applied to a metal target overlying the wafer in the presence of a carrier gas, such as argon. PVD processes typically rely upon a very narrow angular distribution of ion velocity to deposit metal onto sidewalls and floors of high aspect ratio openings in the wafer. The deposition of sufficient material on the sidewalls relative to the amount deposited on the floors of the openings presents a problem. Another problem pertains to avoiding pinch-off of the opening due to faster deposition near the top edge of the opening. As miniaturization of feature sizes has progressed, the aspect ratio (depth/width) of a typical opening has increased, with microelectronic feature sizes having now been reduced to about 22 nanometers. With greater miniaturization, it has become more difficult to achieve minimum deposition thickness on the sidewall for a given deposition thickness on the floor or bottom of each opening.
The increased aspect ratio of the typical opening has been addressed by further narrowing of the ion velocity angular distribution, by increasing the wafer-to-sputter target distance (e.g., to 300 mm or more) and reducing the chamber pressure (e.g., to less than 1 mT). This has given rise to a problem observed in thin film features near the edge of the wafer: At extremely small feature sizes, a portion of each high aspect ratio opening sidewall is shadowed from a major portion of the target because of the greater wafer-to-target gap required to meet the decreasing feature size. This shadowing effect, most pronounced near the wafer edge, makes it difficult if not impossible to reach a minimum deposition thickness on the shadowed portion of the side wall. With further miniaturization, it has seemed a further decrease in chamber pressure (e.g., below 1 mT) and a further increase in wafer-sputter target gap would be required, which would exacerbate the foregoing problems.
Current RF and VHF capacitive source designs utilize asymmetric feed designs. It has been seen that asymmetry of the feed design leads to asymmetry of the electric field at the target surface. This asymmetry at the target or powered electrode invariably results in asymmetry of the deposition or etching of the wafer. Controlling aspect ratios of the feed design is insufficient to negate the asymmetry. The asymmetry, also referred to as “skew”, can become a controlling factor. Therefore, there is a need in the art for systems and methods to mitigate the skew.